ASIC Design Verification Engineer



Advert ID




Job Type




Salary Range

Up to USD0.00 per year

No. of Openings


Branch Information

Minnesota Engineering - (USA) 3600 Minnesota Drive Suite 850 MN Edina , MN 55435



Job Description

Our client is seeking an ASIC Design Verification Engineer to join their team on a contract basis to start out with. This position will have a key role in the development of advanced verification environments for complex SoC components, while ensuring on time delivery with best-in-class quality. Typical tasks include; the development of new environments, execution of verification plans while collaborating with design teams, and debugging complex problems. Candidates must be familiar with constrained random verification and functional coverage closure. This position is located in Minneapolis, MN.

Position Responsibilities:

* ASIC/FPGA DV experience with UVM methodologies

* Experience in developing UVM-based SV test-benches.

* Experienced with defining block, sub-system or SOC top level test plans.

* Hands-on experience with verification environments, architecture definitions and development.

* Relevant experience with one or more of PCIe, NVMe and CPU sub-systems.

* Understanding and knowledge of verification methodologies, flows and quality metrics.

* Team player with great interpersonal communication skills.

Position Qualifications:

* MS or BS in Electrical Engineering, Computer Engineering or Computer Science

* Minimum of 7 years of combined design and verification engineering experience

* Strong leadership and communication skills, with the ability to convey complex technical concepts to other peers in verbal and written form

* A proven ability to achieve results in a fast paced, dynamic environment