Staff RTL Engineer

Industry

Manufacturing and Production

Advert ID

FOX_BBBH23705

Location

Redmond

Job Type

Permanent

Hours

Full-Time

Salary Range

USD130000.00-160000.00 per yea

No. of Openings

1

Branch Information

Pacific Northwest Engineering - (USA) 11245 Southeast 6th Street Suite 200 WA Bellevue , WA 98004

ContactNumber

425-372-2900

Job Description

Job Title: Sr. RTL Engineer



Location: Greater Seattle Area (Relocation Provided)



Employment Category: Direct Hire



Salary Offering: $160,000.00 (Salary Negotiable - Signing Bonus Allocated)



Citizenship: No Citizenship Requirement



Benefits Offered: Medical - Dental - Vision - Retirement Savings - ESPP



Onboarding Requirement: Background & Drugscreen



Projected Start Date: ASAP



Position Summary:



As a Sr. Staff RTL Engineer, you will bring your knowledge and visualization to designing sample hardware, supported integration efforts, and developing on sample hardware. You will also work in partnership with an energetic team and lead a smaller less experienced project team.



Essential Duties and Responsibilities:





* Design, implement and test RTL features.

* Write detailed implementation requirements from high level specifications.

* Document test and implementation plan and then execute on it.

* Work with other teams integrate developed features into prototype hardware.

* Guide more junior members of RTL and integration teams to complete tasks.

* Support bringing up RTL features developed by the team.



Minimum Qualifications: (Knowledge, Skills, and Abilities)





* BS in Electrical Engineering or related field



* Having the capacity to lead a smaller group of engineers along with working independently regarding new work flow.



* At least 12+ years of experience or equivalent combination of education and experience.

* Knowledge of System Verilog, Verilog, Python, TCL programming languages.

* Ability to work well in a fast moving and complex environment.

* Proficient in FPGA Design methodologies from state machine design to DSP implementation.

* Experienced in closing timing in FPGA designs.

* Mapping algorithms to FPGA appropriate logic implementations.



Preferred Qualifications:





* Ability to break down complicated RTL features into smaller design blocks.

* Experiences in a Linux development environment.

* Proficient in FPGA Design methodologies from state machine design to DSP implementation.

* Outstanding verbal, written and presentations skills.

* Simulink DSP integration experience.